datasheet loco? pll cloc k multiplier ics501 idt? / ics? loco? pll clock multiplier 1 ics501 rev p 051507 description the ics501 loco tm is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. the name loco stands for low cost oscillator, as it is designed to replace crystal oscillators in most electronic systems. using phase-locked loop (pll) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 160 mhz. stored in the chip?s rom is the ability to generate nine different multiplication factors, allowing one chip to output many common frequencies (see table on page 2). the device also has an output enable pin which tri-states the clock output when the oe pin is taken low. this product is intended for clock generation. it has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. for applications which require defined input to output skew, use the ics570b. features ? packaged as 8-pin soic, msop, or die ? available in rohs 5 (green) or rohs 6 (green and lead free) compliant packaging ? idt?s lowest cost pll clock ? zero ppm multiplication error ? input crystal frequency of 5 - 27 mhz ? input clock frequency of 2 - 50 mhz ? output clock frequencies up to 160 mhz ? extremely low jitter of 25 ps (one sigma) ? compatible with all popular cpus ? duty cycle of 45/55 up to 160 mhz ? nine selectable frequencies ? operating voltage of 3.3 v or 5.0 v ? tri-state output for board level testing ? 25 ma drive capability at ttl levels ? ideal for oscillator replacement ? industrial temperature version available ? advanced, low-power cmos process block diagram clk pll clock multiplier circuitry and rom crystal or clock input gnd oe vdd crystal oscillator s1:0 x1/iclk x2 optional crystal capacitors 2
ics501 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 2 ics501 rev p 051507 pin assignment clock output table 0 = connect directly to ground 1 = connect directly to vdd m = leave unconnected (floating) common output frequency examples (mhz) pin descriptions x1/iclk vdd gnd oe s1 s0 clk x2 1 2 3 4 8 7 6 5 8 pin (150 mil) soic s1 s0 clk minimum input 0 0 4x input per page 5 0 m 5.3125x input 20 mhz 0 1 5x input per page 5 m 0 6.25x input 4 mhz m m 2x input per page 5 m 1 3.125x input 8 mhz 1 0 6x input per page 5 1 m 3x input per page 5 1 1 8x input per page 5 output 20 24 30 32 33.33 37.5 40 48 50 60 62.5 input 10 12 10 16 16.66 12 10 12 16.66 10 20 selection (s1, s0) m, m m, m 1, m m, m m, m m, 1 0, 0 0, 0 1, m 1, 0 m, 1 output 64 66.66 72 75 80 83.33 90 100 106.25 120 125 input 16 16.66 12 12 10 16.66 15 20 20 15 20 selection (s1, s0) 0, 0 0, 0 1, 0 m, 0 1, 1 0, 1 1, 0 0, 1 0, m 1, 1 m, 0 pin number pin name pin type pin description 1 xi/iclk input crystal connection or clock input. 2 vdd power connect to +3.3 v or +5 v. 3 gnd power connect to ground. 4 s1 tri-level iinput select 1 for output clock. connect to gnd or vdd or float. 5 clk output clock output per table above. 6 s0 tri-level input select 0 for output clock. connect to gnd or vdd or float. 7 oe input output enable. tri-states clk output when low. internal pull-up. 8 x2 output crystal connection. leave unconnected for clock input.
ics501 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 3 ics501 rev p 051507 external components decoupling capacitor as with any high-performance mixed-signal ic, the ics501 must be isolated from system power supply noise to perform optimally. a decoupling capacitor of 0.01f must be connected between vdd and the gnd. it must be connected close to the ics501 to minimize lead inductance. no external power supply filtering is r equired for the ics501. series termination resistor a 33 ? terminating resistor can be used next to the clk pin for trace lengths over one inch. crystal load capacitors the total on-chip capacitance is approximately 12 pf. a parallel resonant, fundamental mode crystal should be used. the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimmi ng process, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) between the crystal and device. crystal capacitors, if needed, must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -12 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each crystal capacitor would be 8 pf [(16-12) x 2 = 8]. absolute maximum ratings stresses above the ratings listed below can cause perm anent damage to the ics501. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature (commercial) 0 +70 c ambient operating temperature (industrial) -40 85 c power supply voltage (measured in respect to gnd) +3.0 +5.25 v
ics501 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 4 ics501 rev p 051507 dc electrical characteristics vdd=5.0 v 5% , ambient temperature -40 to +85 c, unless stated otherwise parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 5.25 v input high voltage, iclk only v ih iclk (pin 1) (vdd/2)+1 v input low voltage, iclk only v il iclk (pin 1) (vdd/2)-1 v input high voltage v ih oe (pin 7) 2.0 v input low voltage v il oe (pin 7) 0.8 v input high voltage v ih s0, s1 vdd-0.5 v input low voltage v il s0, s1 0.5 v output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25 ma 0.4 v idd operating supply current, 20 no load, 100m 20 ma short circuit current clk output + 70 ma on-chip pull-up resistor pin 7 270 k ? input capacitance, s1, s0, and oe pins 4, 6, 7 4 pf nominal output impedance 20 ?
ics501 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 5 ics501 rev p 051507 ac electrical characteristics vdd = 5.0 v 5% , ambient temperature -40 to +85 c, unless stated otherwise note 1: measured with 15 pf load. thermal characteristics for 8soic thermal characteristics for 8msop parameter symbol conditions min. typ. max. units input frequency, crystal input f in 527mhz input frequency, clock input f in 250mhz output frequency, vdd = 4.75 to 5.25 v f out 0 c to +70 c13 160mhz -40 c to +85 c 13 140 mhz output frequency, vdd = 3.0 to 3.6 v f out 0 c to +70 c13 100mhz -40 c to +85 c13 90mhz output clock rise time t or 0.8 to 2.0 v, note 1 1 ns output clock fall time t of 2.0 to 8.0 v, note 1 1 ns output clock duty cycle t od 1.5 v, up to 160 mhz 45 49-51 55 % pll bandwidth 10 khz output enable time, oe high to output on 50 ns output disable time, oe low to tri-state 50 ns absolute clock period jitter t ja deviation from mean + 70 ps one sigma clock period jitter t js 25 ps parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w thermal resistance junction to top of case jt still air 20 c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 95 c/w thermal resistance junction to case jc 48 c/w
ics501 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 6 ics501 rev p 051507 package outline and package dimensions (8-pin msop, 3.00 mm body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e1 e seating plane a 1 a a 2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a--1.10--0.043 a1 0 0.15 0 0.006 a2 0.79 0.97 0.031 0.038 b 0.22 0.38 0.008 0.015 c 0.08 0.23 0.003 0.009 d 3.00 basic 0.118 basic e 4.90 basic 0.193 basic e1 3.00 basic 0.118 basic e 0.65 basic 0.0256 basic l 0.40 0.80 0.016 0.032 0 8 0 8 aaa - 0.10 - 0.004
ics501 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 7 ics501 rev p 051507 package outline and package dimensions (8-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.33 0.51 .013 .020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 l 0.40 1.27 .016 .050 0 8 0 8
ics501 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 8 ics501 rev p 051507 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both ac curacy and reliability, integrat ed device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for us e in normal commercial applications. any ot her applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommen ded without additional pr ocessing by idt. i dt reserves the right to change any circuitry or specificat ions without notice. idt does not authorize or warrant any idt product for use in life suppor t devices or critical medical instruments. part / order number marking shipping packaging package temperature ics501m ics501m tubes 8-pin soic 0 to +70 c ics501mt ics501m tape and reel 8-pin soic 0 to +70 c ics501mi ics501i tubes 8-pin soic -40 to +85 c ics501mit ics501i tape and reel 8-pin soic -40 to +85 c ics501mlf 501mlf tubes 8-pin soic 0 to +70 c ICS501MLFT 501mlf tape and reel 8-pin soic 0 to +70 c ics501milf 501milf tubes 8-pin soic -40 to +85 c ics501milft 501milf tape and reel 8-pin soic -40 to +85 c ics501g 501g tubes 8-pin msop 0 to +70 c ics501gt 501g tape and reel 8-pin msop 0 to +70 c ics501gi 501gi tubes 8-pin msop -40 to +85 c ics501git 501gi tape and reel 8-pin msop -40 to +85 c ics501glf 501gl tubes 8-pin msop 0 to +70 c ics501glft 501gl tape and reel 8-pin msop 0 to +70 c ics501gilf 1gil tubes 8-pin msop -40 to +85 c ics501gilft 1gil tape and reel 8-pin msop -40 to +85 c ics501-dwf - die on uncut, probed wafers 0 to +70 c ics501-dpk - tested die in waffle pack 0 to +70 c ics501e-dpk - tested die in waffle pack 0 to +70 c
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